The present invention concerns an improved physical layer architecture for use in a computer system. The invention is particularly useful for enchancing the performance of a physical layer implementing a bus topology, but may also be used to enhance performance of other interconnection topologies as a ring topology or a circuit switched topology.
In computer systems, a bus is an interconnection topology commonly used to communicate between logical blocks or modules. The modules connect to a common media, such as a set of printed circuit board traces of wires. The rules that govern the access of modules to the bus and the data trransfer constitute the bus protocol. Generally, all modules on a bus must use the same protocol.
A typical implementation of a bus consists of a set of traces embedded in print circuit (PC) board. Modules connect to the bus through bus transceivers. Modules connected to a bus may all reside on the same PC board. Alternately, modules of a bus may reside on separate PC boards and be attached to the electro-mechanical structure that incorporates the physical media of the bus through a series of connectors. The electro-mechanical structure that incorporates the physical media of the bus is called a bus backplane. Various standards have been developed which defined the physical features of the backplane and the bus protocols. These bus standards include VME, Futurebus, Multibus, Nubus. The use of such bus standards allows for end users to configure their own computer systems on a single bus backplane to be able to use a variety of modules designed by many different vendors.
Typically in the physical architecture of a microcomputer, the bus backplane is incorporated on the main PC board, called the mother board, that houses the logic for the microcomputer. Plug-in modules, some of which are referred to as daughter boards, are attached to the mother board using connectors. The plug-in modules may include, for example, PC boards which include memory, a controller for a disk drive, a controller for an interface to a physical layer of an interconnection topology, logic that controls a serial port and/or logic that controls a parallel port.
In general, for communication between the modules of a computer system, bus topologies are preferred to other topologies such as ring topologies or switched topologies for a number of reasons. For example, Bus protocols are generally much simpler than protocols for other topologies. Also, bus topologies are highly configurable. That is, each slot position on a bus to which a module may be added is equally connected to modules on all other slots on the bus. Additionally, bus topologies are inexpensive. The common media consists only of metal lines and connectors. Each slot of the bus slot is sufficiently inexpensive to provide that the incremental expense for providing unused slots is not prohibitive.
However there are certain practical limitations to the use of bus topologies. For example, the capacitive loading on a bus due to the attached modules greatly increases the propagation delay. This directly affects the data transfer rate in most types of data transfer protocols, for example synchronous protocols in which data transfers are centrally clocked, and in compelled asynchronous protocols which require a handshake on every data transfer. The only data transfer type which is not impacted by the bus round trip delayed caused by capacitive loading is uncompelled source synchronous bus transfers in which a long burst transfer is clocked by the sender. In such a transfer the data transfer rate is only limited by skews between bits of data and strobe.
The capacitive loading also decreases the impedance of a bus line to a very low value, i.e., approximately 20 ohms. Since a bus driver on the bus sees half the bus impedance, i.e., 10 ohms, high currents are required to drive the bus at full speed. For example, a three volt swing on the bus which is typical for TTL, will require 300 milliamps (3 volts divided by 10 ohms) to drive the bus on the first transition with proper termination. Since most bus drivers are rated only at 50 to 100 milliamps, the bus is typically under terminated and dependent on reflections to build up the signal to the final level. The reflections take one or more bus round trip delays to settle resulting in a settling time delay that is a significant portion of the transfer cycle time for a bus.
The settling time penalty can be avoided by driving the bus properly with full termination. This can be done by increasing the drive current, which unfortunately significantly increases the power and noise in the system. Also, higher current bus drivers have larger output capacitance which further reduces bus impedance. Alternately, the settling time penalty can be avoided by reducing the voltage swing. For example, the bus can be implemented using Backpane Transceiver Logic (BTL) which uses lower capacitance transceivers to reduce bus loading and uses lower signal levels to reduce the required amount of drive current to an acceptable level (i.e., 50 to 100 mA) while still driving the bus under full loading on the first transition (without reflections). Eliminating the settling time of the bus significantly improves the data transfer rate on state-of-the-art buses. Typically this improvement is 50%.
The high current required for driving the bus not only take a lot of power, but also limit the number of transceivers that can be incorporated in a single integrated circuit due to the power dissipation limits of the integrated circuit package. Typically, each integrated circuit is limited to eight to ten transceivers. Consequently, wide data/address fields and the associated synchronization signal require multiple integrated circuits for transceivers. For example, five to six integrated circuits containing transceivers may be necessary for a 32 bit bus which includes control bits and a clock. Dfferences in propagation delay (skew) between transceivers in different chips due to process, temperature and supply voltage variations require that a synchronization signal be delayed by the amount of the skew in order to guarantee that data sent across the bus is valid before a synchronization pulse arrives at the bus receiver. This delay is a significant factor limiting the maximum data rate on buses.